This patent application claims priority based on a Japanese patent application, H10-368154 filed on Dec. 24, 1998, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a memory device testing apparatus for testing a memory device. In particular, the present invention relates to a memory device testing apparatus comprising a failure analysis memory unit that can change the dividing method of an address space of a data storing memory.
2. Description of the Related Art
FIG. 1 shows a block diagram of a conventional memory 10 in a failure analysis memory unit for storing fail data output from a comparator. This memory 10 has a data storing memory 12, a compact memory 14, a compact memory address generator 16, and a bus controller 18. The data storing memory 12 has at least two memories and has the same word number and bit size as the entire memory under test. The compact memory 14 has an extremely small capacity compared to the data storing memory 12. The data storing memory 12 is divided into a plurality of partial address spaces for future failure analysis of the memory under test. The compact memory 14 has a plurality of addresses, each corresponding to a plurality of the partial address spaces of the data storing memory 12.
In the memory device testing apparatus, fail data, which is output from the comparator, and an address signal, which indicates the address for storing the fail data, are input to the memory 10. A lower address signal 20 constituted by a lower bit of the address signal is input to the address pin (AD) and the compact memory address generator 16. Furthermore, an upper address signal 22 constituted by an upper bit of the address signal is input to the chip select pin (CS) of the data storing memory 12 and the compact memory address generator 16. Using the upper address signal 22, one of a plurality of memories, which constitutes the data storing memory 12, is selected. The compact memory address generator 16 generates an address which accesses the compact memory 14 based on the lower address signal 20 and the upper address signal 22. This address corresponds to the partial address space of the data storing memory 12.
A write control signal 24 is input to the write enable pin (WE) of the data storing memory 12 and the compact memory 14. The bus controller 18 outputs the fail data signal 26 to the data storing memory 12 and the data input pin (DI) of the compact memory 14. In the conventional memory 10, by inputting the above signals to the data storing memory 12 and the compact memory 14, the fail data is input to the data storing memory 12, and the failure information is written into the compact memory 14. The failure information indicates that there is a failure spot in the partial address space.
Recently, high-capacity, highly integrated memory devices have been developed. The memory to be tested by the memory device testing apparatus may often be a newly developed bulk memory. If the memory device as a whole is determined a failure when there is even just one failed cell inside the high-capacity, highly integrated memory device, the yield factor is very low. Therefore, there is a method of replacing the failed cell with a spare memory cell by providing the memory device with spare cells beforehand. According to this method, by replacing the failed cell with a spare cell during the manufacturing process of the memory device, a memory device that is not considered a complete failure can be manufactured.
As one of the means of replacement of the failed cell using the above method, a memory failure relief analyzer is provided on the memory device testing apparatus. This memory failure relief analyzer retrieves the address of the failed cell in the memory device and finds a solution such designation of the spare cell to be used for replacing the retrieved failed cell. The memory failure relief analyzer receives the fail data from the data storing memory 12 based on the failure data stored in the compact memory 14 of the failure analysis memory unit. If the failure information is stored in the address of the compact memory 14, the memory failure relief analyzer receives the data in the corresponding partial address space of the data storing memory 12. Contrary to this, if the failure information is not stored in the address of the compact memory 14, the memory failure relief analyzer does not receive the data in the corresponding partial address space of the data storing memory 12.
The failure analysis memory unit and the memory failure relief analyzer can exist as different units and can be connected to each other by a cable. By using the information stored in the compact memory 14, unnecessary data is not transferred. This reduces the data transfer time due to the cable provided between the failure analysis memory unit and the memory failure relief analyzer.
According to the configuration of the conventional memory 10 shown in FIG. 1, the fail data can be written into the compact memory 14 only when the memory under test is actually being tested. Therefore, when changing the dividing method of the address space of the data storing memory 12 and writing the failure data for every partial address space in the compact memory 14, the memory under test has to be tested repeatedly with each change in the settings of the compact memory address generator 16. Generally, the checks on writing/reading for each memory cell and the checks for interference with other nearby memory cells are carried out during the testing of the memory itself. Therefore, if the number of addresses in the memory under test is N, the time for testing the memory under test is proportional to approximately the square of N.
Depending on the dividing method of the address space of the data storing memory 12, the failure information will be stored in many or all of the addresses in the compact memory 14. In this situation, all the memory data stored in the data storing memory 12 is transferred to the memory failure relief analyzer. Therefore, the data transfer time from the failure analysis memory unit to the memory failure relief analyzer cannot be reduced. It is therefore less useful to provide the compact memory 14 in the memory 10.
Furthermore, according to the configuration of the conventional memory 10, the memory under test has to be tested again to change the dividing method of the address space of the data storing memory 12, and to write the failure information of every new partial address space into the compact memory 14. Because this re-testing takes so much time, it is not the preferred method for changing the dividing method of address space and re-generating the data of the compact memory 14.
Therefore, it is desired to provide a failure analysis memory unit which can change the dividing method of the address space of the data storing memory 12 without re-testing of the memory device testing apparatus. Furthermore, for a purpose other than the memory failure relief, by making the dividing method of the address space changeable, the memory device testing apparatus can be highly versatile with wider applications.
Therefore, it is an object of the present invention to provide a memory device testing apparatus having a failure analysis memory unit which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a memory device testing apparatus for testing a memory device can be provided. The memory device testing apparatus comprises: a pattern generator which generates an address signal that indicates an address of the memory device, an input pattern signal to be input to the memory device, and an expectation value pattern signal to be read out from the memory device based on the input pattern signal; a signal input/output unit which provides the input pattern signal to the address indicated by the address signal of the memory device and outputs an output pattern signal from the address of the memory device; a comparator which compares the output pattern signal output from the memory device with the expectation value pattern signal output from the pattern generator and outputs fail data which indicates the existence of a failure when there is a failure spot in the memory device; and a failure analysis memory unit which has: a data storing memory, in which the fail data output from the comparator is written into an address corresponding to the address of the failure spot in the memory device, and a compact memory in which the failure information, which indicates that there is the failure spot in the memory device, is written based on the fail data that was already written into the data storing memory.
The memory device testing apparatus can be provided such that the failure analysis memory unit may have a compact memory address generator which sets a dividing method for dividing the data storing memory into at least two divided address spaces. The compact memory address generator may generate addresses of the compact memory corresponding to each of the divided address spaces. The failure analysis memory unit may have a data line for inputting the fail data, which is written into the data storing memory, to the address of the compact memory generated by the compact memory address generator.
The memory device testing apparatus can be provided such that the failure analysis memory unit may have a bus controller which outputs a read control signal to the data storing memory and outputs a write control signal to the compact memory. The failure analysis memory unit may have a multiplexer which outputs to the compact memory either the fail data already written into the data storing memory or the fail data to be written to the data storing memory. The failure analysis memory unit may have a data processor which receives memory data output from the data storing memory. The data process or provides the fail data to the compact memory when the data processor detects that the received memory data is fail data.
According to the second aspect of the present invention, a memory device testing method which tests a memory device using data storing memory that stores data can be provided. The memory testing method comprises steps of generating an address signal which indicates an address of the memory device and an input pattern signal to be input to the memory device; providing the input pattern signal to the address indicated by the address signal of the memory device; outputting fail data, which indicates the existence of a failure, if there is a failure spot in the memory device when comparing the output pattern signal output from the address of the memory device based on the input pattern signal, with an expectation value pattern signal to be read out from the memory device based on the input pattern signal; writing the output fail data into an address of the data storing memory which corresponds to the address having the failure spot in the memory device; and writing failure information, which indicates that there is a failure spot in the memory device, into a compact memory having a smaller capacity than the data storing memory based on the fail data that was previously written to the data storing memory.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.